The present invention relates to semiconductor devices and, more particularly, to CMOS semiconductor devices in which bias voltages different from the power supply potential and ground potential are applied to the substrates.
In CMOS semiconductor devices, to reduce the power consumption while maintaining high-speed operation, integrated circuits are designed using field effect transistors with low threshold voltages and low supply voltages.
In some devices, to decrease the current in the stand-by state of the circuit, i.e., so-called leakage current, or to compensate for variations in the threshold voltages during the operation of the circuit, substrate bias voltages different from the power supply potential and ground potential are applied.
In such devices, the lines for applying the substrate or well potential are not connected to the power supply lines or the ground line. For this reason, during the power on sequence when the operation of the substrate potential control circuit is still unstable, latch-up could occur because the power supply voltage could become higher than the substrate potential. To prevent this, each substrate is connected with an appropriate potential until a predetermined time period from the onset of the power-on elapses.
However, when the device has a plurality of the supply voltages, latch-up occurs during the power-on process, as will be described later.